As semiconductor devices become more highly integrated, the size of a transistor has been reduced, and the integration density of DRAM cells have increased, e.g., producing 1 giga-bit DRAM cells on a large scale.
Generally, a DRAM cell includes a single transistor and a capacitor, and the single-transistor DRAM cell requires the capacitor to store a sufficient charge to allow the cell state to remain true between refresh cycles. Further, a DRAM cell can be categorized as either a stacked cell or a trench cell depending on the method used in forming the cell capacitor. Referring to a stacked DRAM, there have been various approaches used to obtain a cell capacitor that occupies a smaller area to comply with a reduction in a design rule. For example, a method of increasing the height of a storage electrode of a capacitor, a method of increasing an effective surface area using hemispherical grains (HSG), and a method of utilizing both the inner and the outer areas of a cylinder through a capacitor of one cylinder storage (OCS) have been widely developed. In particular, it has been proposed that an OCS capacitor is the most likely type of capacitor to occupy a smaller area to comply with a future reduction in a design rule.
However, a conventional OCS capacitor causes twin bit failure. Twin bit failure occurs when a capacitor electrode in a DRAM cell falls down and contacts another capacitor electrode of another DRAM cell, thereby causing each DRAM cell to fail. In other words, a cylindrical capacitor electrode is prone to fall down when storage electrodes are 2-dimensionally disposed and a space interval therebetween is sharply reduced due to a reduction in the design rule.
FIG. 1 is a top plan view illustrating a semiconductor device with a conventional storage electrode.
Referring to FIG. 1, conventional storage electrodes 50 of an OCS capacitor are arranged at right angles to each other in a direction of a bit line 30 and a word line, i.e., a gate line 20. In a top plan view, storage electrodes 50 may be formed as rectangles, each of the storage electrodes having a major axis, e.g., in a direction of the bit line 30, and are disposed to be adjacent to each other in a direction of the bit line 30. In addition, the right-angled edges may be rounded as shown in FIG. 1. Further, the storage electrodes 50 formed as rectangles have a minor axis, e.g., in a direction of the gate line 20, and are disposed to be adjacent to each other in a direction of the gate line 20.
In a DRAM cell having a rectangular electrode and complying with a design rule of 0.1 μm, the size of the rectangle electrode in the major-axis direction would be about 300 nm and in the minor-axis direction would be about 120 nm. Therefore, a space interval between the storage electrodes 50 is no more than about 80 nm. Further, the height of the storage electrode 50 should be about 1500 nm to secure the capacitance required of a DRAM.
Accordingly, the height/width ratio of the cylindrical storage electrode 50 becomes 12 or more. Thus, the cylindrical storage electrode 50 is highly susceptible to falling down. When the storage electrodes 50 lean or fall, the storage electrodes come into contact with each other due to the very narrow space interval of 80 nm therebetween. Thus, a twin bit failure is experienced. As the design rule of a DRAM cell is reduced, e.g., to about 100 nm or less, the likelihood of the twin bit failure between storage electrodes also increases.
It has been recognized that the collapse of the storage electrodes 50 results from the arrangement of the storage electrodes 50 as illustrated in FIG. 1. For this reason, there have been many attempts to change the arrangement of the storage electrodes 50 to increase the space interval therebetween.
When the storage electrodes 50 are arranged as shown in FIG. 1, the storage electrodes 50 can be aligned with the contact bodies, which electrically connect the storage electrodes 50 with an active region 11, defined by a device isolation region 15 of a semiconductor substrate. However, if the arrangement of the storage electrodes 50 is altered, the contact bodies cannot be appropriately aligned with the storage electrodes 50. As illustrated in FIG. 1, in a conventional method, the storage electrodes 50 overlap the conductive buried contact pads 41, which are formed on the active region 11 of the semiconductor substrate. Further, if the storage electrodes 50 are arranged differently, the storage electrodes 50 may be misaligned with the conductive buried contact pads 41.
The conventional storage electrodes 50 are electrically connected to the active region 11 by buried contact pads 41 formed on the active region 11 of the semiconductor substrate and storage electrode contact bodies (not shown) formed thereon, for example, buried contacts. As illustrated in FIG. 1, when a center of the storage electrode 50 coincides with that of the buried contact pad 41, the storage electrode contact body may be formed between the storage electrode 50 and the buried contact pad 41 such that the center of the storage electrode contact body coincides with that of the buried contact pad 41. However, as described above, if the center of the storage electrode 50 is misaligned with the buried contact pad 41, it becomes difficult to align the center of the storage electrode 50 with that of the storage electrode contact body. Thus, the contact area between the storage electrode 50 and the storage electrode contact body is reduced, thereby causing defects due to an increase in the contact resistance.
Therefore, there is a need for a storage electrode contact body (not shown), i.e., a buried contact, having a new structure to be disposed between the conductive buried contact pad 41 and the storage electrode 50.
Further, a conductive direct contact pad 45 is disposed around the conductive buried contact pad 41. The conductive direct contact pad 45 is spaced apart from the conductive buried contact pad 41 and is used as a medium to electrically connect the active region 11 of the semiconductor substrate with a bit line 30. Thus, the storage electrode contact body, i.e., the buried contact with a new structure, which will be disposed between the conductive buried contact pad 41 and the storage electrode 50, should be sufficiently spaced apart from the direct contact pad 45 to prevent any defects from occurring, e.g., a short circuit. Therefore, it is very difficult to dispose the storage electrode contact body or the buried contact with the new structure with a wider width to be aligned to the storage electrodes disposed in the new arrangement.
Accordingly, the storage electrode contact body should have a new structure to enable a smooth electrical connection between the storage electrodes 50 and the active region 11 of the semiconductor substrate. This makes it possible to change the planar structure of the storage electrode 50 or the arrangement of the adjacent storage electrodes 50 to prevent a collapse of the storage electrodes 50 of the OCS capacitor. In addition, the new storage electrode contact bodies should be embodied in consideration of a misaligned margin or an overlay margin between layers. In addition, to enhance process feasibility, a resolution limit in a photolithography process should be considered with a reduction in a design rule.
Therefore, a need exists for increasing the contact area between a storage electrode contact body and a storage electrode of a capacitor in a semiconductor device to prevent such occurrences as twin bit failure.